1. Field of the Invention
The present disclosure generally relates to techniques for testing semiconductor devices, and, more particularly, to techniques for testing integrated circuits that include logic circuitry portions and embedded memory portions with memory built-in self-test logics connected thereto.
2. Description of the Related Art
In manufacturing semiconductor devices including relatively complex circuitry, the testing of the device may represent a part of the manufacturing process, which is frequently underestimated in terms of cost and effort required to obtain reliable data with respect to proper functionality and reliability of the device. One reason in failing to meet performance specifications of the integrated circuit may reside in design errors that may be identified and remedied by circuit verification on the basis of software simulation and/or prototype testing prior to mass production of the integrated circuits under consideration. An improper functionality of the integrated circuit may further be caused by the manufacturing process itself when the completed circuitry does not correspond to the verified circuit design owing to process fluctuation in one or more of the very large number of process steps. Although measurement and test procedures are incorporated at many points in the manufacturing process, it is nevertheless extremely important to ascertain the correct functioning of the final semiconductor device, since, according to a common rule of thumb, the costs caused by defective chips increase with each assembly phase by approximately one order of magnitude. For example, the costs caused by a defective circuit board including a faulty chip are typically significantly higher than identifying a defective chip prior to shipping and assembling the circuit board. The same holds true for a system, when a failure thereof is caused by one or more defective circuit boards, as a downtime of an industrial system may result in averaged costs of approximately several hundred dollars per minute compared to a price of a few dollars for an integrated circuit chip having caused the defect.
Hence, there is a vital interest in developing test procedures to identify as many defects as possible in completed integrated circuits while not unduly increasing the total manufacturing costs. In particular, with the demand for more features and lower costs of circuits, there is a tendency to integrate a plurality of different circuit portions into a single chip to provide a complete system on a chip (SOC). A semiconductor device comprising various functional blocks may typically include, in addition to one or more logic blocks, one or more embedded memory portions, such as are used as on-chip cache for CPUs or as buffers for data packets that are transferred between different clock domains.
As discussed above, economic constraints force semiconductor manufacturers to not only minimize the defect level of the total manufacturing process, but also to provide, in combination with a reduced defect level, a high fault coverage so as to reduce the delivery of defective chips at reasonable cost for appropriate test procedures and techniques. For moderately complex integrated circuits, it has become standard practice to develop the basic design of the circuit while taking into consideration a plurality of constraints posed by effective test procedures. Moreover, typically, additional hardware resources are provided in the chip that may enable the identification of faulty circuit components for a broad class of operating conditions, wherein the additional hardware resources in combination with design specifics of the basic circuit and sophisticated test procedures and test patterns substantially determine the fault coverage of the test procedure.
In many circuit designs, the functional logic portion is tested by so-called scan chains, which represent a chain of flip-flops connected to a specific area of the functional logic in such a way that the functional logic or a specific area thereof may be initialized with a desired state that has previously been entered into the scan chain. Moreover, upon providing one or more clock signals to the functional logic, the state thereof, that is the state of each logic gate connected to a dedicated flip-flop of the scan chain, may then be stored in the scan chain and may be shifted out by supplying respective shift clock signals to the scan chain. Depending on the bit pattern or input vector entered into the scan chain for initializing the functional logic, corresponding faulty logic gates may be identified. However, the fault coverage, i.e., the potential for identifying any error within the functional logic, significantly depends on the design, selection and number of appropriate scan chains and suitable input vectors. In principle, such scan test techniques may also be modified so as to include the testing of memory portions, wherein, however, only for small memories, appropriate scan test patterns, i.e., the number and size of appropriate input vectors, may exhibit a size that allows the testing of memory portions within acceptable time intervals.
For this reason, frequently, a so-called memory built-in self-test (MBIST) logic is provided as an additional hardware resource within a chip to implement a memory test procedure requiring fewer clock cycles and supporting the testing of important extended fault models that are specific to memories. With reference to FIGS. 1a-1b, the configuration and the test procedures for a representative conventional semiconductor device including functional logic and a memory portion are described in more detail so as to more clearly illustrate the problems involved.
FIG. 1a schematically shows a circuit diagram of a semiconductor device 100 including a functional logic circuitry 110, which may be connected to a memory portion 120 via write lines, read lines and control lines that are commonly referred to as lines 121. The device 100 further comprises an MBIST logic 130 including, for instance, a finite state machine 131 for implementing a desired algorithm for testing the memory portion 120. The MBIST logic 130 further comprises all components required for disconnecting the memory portion 120 from the functional logic 110 so as to enable the operation of the memory portion 120 fully under control of the MBIST logic 130 when operating the logic 130 for the memory test.
On the other hand, when disabled, the MBIST logic 130 is “transparent” for the lines 121 so as to allow proper operation of the logic circuitry 110 in combination with the memory portion 120. The MBIST logic 130 comprises a first control input 132, which is also referred to as MBIST-start, and a second control input 133, also indicated in the drawing as MBIST-enable. Moreover, a first output 134, also referred to in the drawing as MBIST-good, and a second output 135, also indicated as MBIST-done, are provided in the MBIST logic 130. It should be noted that, for convenience, any additional inputs or outputs of the logic 130, such as clock inputs, reset inputs and other control lines, are not shown.
When operating the device 100 in a memory test mode, the MBIST logic 130 may be enabled by providing a corresponding signal at the input 133 (MBIST-enable) to disconnect the memory portion 120 from the surrounding logic circuitry 110. By supplying a corresponding signal at the input 132 (MBIST-start), the circuit portion 130 is started to generate address values and to write data into the memory portion 120. The circuit 130 may also include a comparator, which may be configured to check if the data written into the memory 120 may be correctly read back from the memory, and which may provide a corresponding value at the output 134 (MBIST-good). For instance, the value of the output 134 may show logic “0” as long as no error occurs in writing data into the memory 120 and reading back the data, while the output 134 may be set to a logic “1” once a mismatch between the actually read data and the expected data is detected. After the test of the memory 120 is completed, a corresponding signal may be presented at the output 135 (MBIST-done), for instance, the output 135 may be switched from logic “0” to logic “1” if the test is completed.
Consequently, on the basis of an appropriately designed test algorithm, the memory portion 120 may be tested with respect to any relevant failure types, such as “stuck-at,” “stuck-open,” coupling of memory cells, etc., wherein the built-in test portion 130 may be operated at regular operating speed of the semiconductor device 100. In some cases, the self-test may even be performed on the basis of a clock frequency that may be higher than that of the device 100 at standard operating conditions. It should be appreciated, however, that, at very high frequencies, as may typically be used in modern circuit designs, the failure detection itself, i.e., the comparison between the results of the read operations and the corresponding expected values, i.e., the values previously written into the memory, may take several clock cycles in the internal pipelines of the test circuitry 130. That is, due to the high operating speeds, several stages of processing the relevant signals, such as the bit vectors obtained as read results, providing the comparison result and the like, have to be performed in several stages in order to ensure a reliable signal processing so as to avoid undue errors in obtaining the global memory test results. Thus, upon completing the memory self-test on the basis of an appropriate algorithm, a global assessment may be obtained on line 134, which may thus represent a simple fail/no fail statement with respect to the functional behavior of the memory portion 120. In some cases, additional information may be provided by the test circuitry 130, for instance in the form of a memory address of the first failure detected when performing the test algorithm in the test circuitry 130. Although the corresponding memory test results may be sufficient for qualifying products prior to shipping the same, additional information may be highly desirable in view of enhancing yield engineering, failure diagnosis and design improvements. For these tasks, a sampling of all failing addresses and bits may be necessary in order to construct a so-called bitmap to determine whether the defects detected follow a specific typographical pattern. For this purpose, the failure data, that is typically the comparator results between expected values and any values read out from the memory portion 120, is transferred to an external test equipment in order to establish a corresponding bitmap and perform additional fault analysis. Hence, for every read operation on the memory under test, the comparator results are conveyed to the chip's periphery on the basis of an appropriate interface.
FIG. 1b schematically illustrates a portion of the semiconductor device 100 in which the test circuitry 130 comprises a comparator unit 136 that received input data, for instance in the form of bit vectors 137, 138, which may represent the results of a read operation performed on the plurality of memory cells and the corresponding expected data, which may represent the bit values for a portion of the memory 120 in a proper functional state when accessed by the read operations. Similarly, the comparator 136 may output a result bit vector 139, which may thus include the comparison results for each of the read operations of the memory cells accessed during one read cycle performed on the memory 120. The corresponding bit vector 139 may be transferred to an interface 140, which may allow access of the semiconductor device 100 by an external test equipment in which a plurality of result vectors 139 may be stored and may be used as a bitmap for evaluating the operational behavior and status of the memory portion 120. In sophisticated semiconductor devices, the memory portion 120 may be operated with clock frequencies of 1 GHz and significantly higher, while a bit width during a corresponding memory access may involve several hundred bits. Consequently, the bandwidth provided by the data path including the interface 140 may not support the operation of the circuitry 130 at the desired high speed when the plurality of continuous read operations are to be performed so that a corresponding adaptation of the bandwidth defined by the interface 140 may have to be guaranteed so as to avoid data corruption. However, a corresponding limitation of data transfer from the internal test circuitry 130 to an external test equipment may be associated with a reduced reliability of the test results since the detection of any failure that may only manifest itself at full speed, such as weak coupling of memory cells, delay dependant faults and the like, are no longer detectable or are detectable with a significantly reduced degree of fault coverage only.
In view of the situation described above, the present disclosure relates to semiconductor devices and methods of operating the same in which failure results of a memory may be obtained on the basis of a device internal test circuitry while avoiding, or at least reducing, the effects of one or more of the problems identified above.